Start a Project

Start your project with ChipFoundry

This guide walks you through the initial steps of setting up a new project with ChipFoundry.

Step 1: Creating Repo from Template

1. Navigate to the caravel user project GitHub repo: On your browser, go to caravel user project repo and click on use template.
2. Rename and Adjust Privacy: You will be redirected to create a repo under your organization, rename for your project and adjust privacy if needed, we support both open-source and private designs.

Step 2: Cloning the Template Repository

1. Get the Repository URL: On your repo page, you should find the URL of the Git repository. Copy this URL. It will likely be an HTTPS or SSH link.
2. Open Your Terminal: Launch your terminal or command prompt on your local machine.
3. Navigate to Your Workspace: Use the cd command to go to the directory where you want to store your project files. For example:

   cd ~/workspace/chipfoundry_projects
   

4. Clone the Repository: Use the git clone command followed by the repository URL you copied:

   git clone <repository_url> your_project_name
   

   Replace <repository_url> with the actual URL and your_project_name with the desired name for your project directory.
5. Navigate into Your Project Directory: Once the cloning is complete, move into your newly created project directory:

   cd your_project_name
   

Step 3: Setting up your Local Environment

1. Setup your environment: Setting up the environment is done using this command:

   make setup
   

   This might take a while, depending on your internet speed.

Step 4: Updating the Verilog Files

1. Locate the Verilog Source Files: Inside your project directory, navigate to the directory containing the Verilog source files under verilog/rtl

   cd verilog/rtl
   

2. Implement Your Design: Replace the example design with your own Verilog code. Ensure your top-level module declaration and port definitions are correct.
3. Add New Verilog Files: If your design consists of multiple modules, create new .v files and add your Verilog code to them. Make sure to instantiate these modules in your top-level design.

Step 5: Updating the OpenLane Configuration Files

1. Navigate to the OpenLane Configuration Directory: Go back to the root of your project directory and then navigate to the OpenLane configuration directory. This is named openlane/<macro_name>.

   cd ../openlane
   

2. Edit the config.json File: Open the config.json file with your text editor. This file contains various configuration parameters for the OpenLane flow.
3. Update Project Information: Modify the DESIGN_NAME parameter to match the name of your top-level Verilog module (without the .v extension).
4. Specify Source Files: Ensure the VERILOG_FILES parameter correctly lists all your Verilog source files, relative to the rtl directory.
5. Adjust Other Parameters (as needed): Review other parameters in the config.json file, such as clock period, floorplanning constraints, and power settings, and adjust them according to your design requirements.

Step 6: Running the OpenLane Flow

1. Install Docker (if not already installed): OpenLane runs within a Docker container. If you don't have Docker installed, follow the instructions on the official Docker website to install it.
2. Navigate to the Project Root: Go back to the root directory of your project in the terminal.

   cd ..
   

3. Run the OpenLane Flow: Execute the OpenLane command to start the synthesis, placement, routing, and other steps of the physical design flow.

   make <macro name>
   

   Replace <macro name> with the macro you want to harden.
4. Monitor the Flow: OpenLane will print output to the terminal as it progresses through the different stages. Pay attention to any error messages.
5. Examine the Results: Once the flow completes (hopefully without errors), the results will be located in the runs directory within your project. You can examine the generated GDSII file, reports, and other output files.

Step 7: Running mpw-precheck

1. Execute the Precheck Tool: Run the precheck tool to check for DRC, LVS, OEB and other checks to make sure that your design will fit into one of our SoC reference designs.

   make run-precheck
   

2. Review the Precheck Report: The precheck tool will generate a report highlighting any potential issues or violations of the chipfoundry design rules. Carefully review this report and address any identified problems by going back and modifying your Verilog code or OpenLane configuration.

By following these steps, you should be well on your way to starting your project with ChipFoundry. After you are done with these steps, you can submit your design to ChipFoundry and get it fabricated!